XRF8 Device Specifications

System-on-Module (SOM) with RF analog I/O, Ultrascale+ RFSoC FPGA, 8GB Memory, QuadMesh Interlink

FEATURES

• Eight 14-bit A/D inputs
• Eight 14-bit D/A outputs
• 700 mVp-p, direct-coupled, 50 ohm inputs
• 700 mVp-p, direct-coupled, 50 ohm outputs
• Xilinx Ultrascale+ ZU47/48 RFSoC/FPGA
• 2 Banks of 64-bit, 4GB DRAM (8 GB total)
• Ultra-low jitter programmable clock
• External reference clock
• Multiboard, phase-aligned external trigger
• Four, independent mesh links each providing 20 Gbps sustained transfer rates
• 4.0" x 5.0" SOM module.
• 40W typical power consumption

APPLICATIONS

• WLAN, WCDMA, WiMAX front end
• Medical Imaging
• RADAR
• High Speed Data Recording and Playback
• IP development
• FrameWork Logic

SOFTWARE

• Petalinux Drivers
• C++ Host Tools

DESCRIPTION

The XRF8 integrates eight (four IQ), digitizing channels and eight (four IQ) waveform generation channels with real-time signal processing on a SOM IO module for demanding, real-time DSP applications. The tight coupling of the analog I/O within the Ultrascale+ RFSoC FPGA core provides low latency, optimized for architectures such as beam-steering, SDR, RADAR, and LIDAR front end sensor digitizing and processing. The Quad Mesh system interface sustains transfer rates at 16 Gbps to four peers concurrently facilitating creation of large meshes within high-performance real-time systems.

The onboard 1517-pin Xilinx ZU47/48 DR with 8 GB external DDR4 RAM addressable as two 64-bit banks, provides a very high performance DSP core. On-chip integration of multichannel, GSPS analog IO, zero-wait SRAM block memory and quad ARM CPU cores enable real-time signal processing at extremely high rates.

The XRF8 exposes all eight of the RFSoC's (10.0 GSPS-capable) D/A channels and eight (5.0 GSPS-capable) A/D channels. On chip mixer and interpolator/decimator capabilities (respectively) can be enabled to implement concurrent, real-time frequency conversions. Sample clocks are generated via a cascaded ultra-low-jitter onboard PLL referenced either via an onboard, programmable 0.2-800 MHz TCXO or externally-supplied reference clock. Phase aligned, synchronous sampling of all channels at full hardware rates across multiple cards is possible if supplied and external reference clock and trigger operating in the reference clock domain.

Software tools for target development include C++ libraries and drivers for Petalinux. Application examples demonstrating the module features and use are provided, including real-time, dynamic DAC waveform generation and analog captures.

ORDERING INFORMATION

Standard Features

Analog Performance

Architecture and Features

The XRF8 module architecture incorporates a Ultrascale MPSoC system-on-chip which incorporates quad ARM processors and dual real-time coprocessors, FPGA computing core, on chip RF analog I/O and Aurora QuadMesh core. These resources are integrated with external DDR4 external memories, ultra-low jitter programmable sample clock, boot flash and power management.

FPGA Core

The XRF8 employs a Zynq Ultrascale+ RFSoC for DSP and control. This system-on-chip FPGA is capable of over 8.2 TeraMACs with over 4200 DSP elements. In addition to the raw processing power, the FPGA fabric integrates logic, memory and connectivity features that make the FPGA capable of applying this processing power to virtually any algorithm and sustaining performance in real-time.

QuadMesh Host Interface

The XRF8 architecture delivers ~ 64 Gbps sustained data rates over QuadMesh using the Aurora protocol. Packet systems can be implemented atop Aurora as an application interface layer to provide efficient, flexible inter-board transfers at high data rates.

Digital IO

72 digital lines are routed directly from the programmable logic (PL) fabric as length-matched differential pairs. These are useful for implementing low-latency state signaling, or interfacing to custom hardware devices via I2C, SPI or other common serial or parallel standards.

Module Management

The module has facilities for temperature monitoring within the FPGA die. The temperature sensor is monitored by a dedicated system monitor IP, so that power shuts when a critical temperature is exceeded.

Logic Tools

High speed DSP, analysis, customized triggering and other unique features may be added to the module by modifying the logic. The Board Support Package (BSP) tool provides support for RTL development. The standard logic provides a hardware interface layer that allows designers to concentrate on the application-specific portions of the design.