DAQ16 Device Specifications

V 1.25 04/23/20

System-on-Module (SOM) with RF analog I/O, Ultrascale+ RFSoC FPGA, 4GB Memory, QuadMesh Interlink

FEATURES

• Sixteen 12-bit A/D inputs
• Sixteen 14-bit D/A outputs
• 1000 mVp-p, direct-coupled, 50 ohm inputs
• 500 mVp-p, direct-coupled, 50 ohm outputs
• Xilinx Ultrascale+ ZU39DR RFSoC/FPGA
• 2 Banks of 64-bit, 2GB DRAM (4 GB total)
• Ultra-low jitter programmable clock
• External reference clock
• "Zero-phase error" external trigger
• Four, independent mesh links each providing 16 Gbps sustained transfer rates
• 4.0” x 5.0” SOM module.
• 40W typical power consumption
• Conduction cooled via cold-plate

APPLICATIONS

• Beam steering
• WLAN, WCDMA, WiMAX front end
• RADAR
• Medical Imaging
• High Speed Data Recording and Playback
• IP development

SOFTWARE

• FrameWork Logic
• Petalinux Drivers
• C++ Host Tools

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The DAQ16 integrates sixteen (eight IQ), digitizing channels and sixteen (eight IQ) waveform generation channels with real-time signal processing on a SOM IO module for demanding, real-time DSP applications. The tight coupling of the analog I/O within the Ultrascale+ RFSoC FPGA core provides low latency, optimized for architectures such as beam-steering, SDR, RADAR, and LIDAR front end sensor digitizing and processing. The Quad Mesh system interface sustains transfer rates at 16 Gbps to four peers concurrently facilitating creation of large meshes within high performance real-time systems.

The onboard 1760-pin Xilinx ZU39DR with 4 GB external DDR4 RAM addressable as two 64-bit banks, provides a very high performance DSP core. On-chip integration of multichannel, GSPS analog IO, zero-wait SRAM block memory and quad ARM CPU cores enable real-time signal processing at extremely high rates.

The DAQ16 can be fully customized using VHDL using the supplied board support package (BSP). The BSP provides standard IP cores for arbitrary waveform playback, and contiguous capture of ADC data of specified length (framed mode) DDR4 memory control and QuadMesh communications.

ORDERING INFORMATION

ILLUSTATION 2: Block diagram detail

Multiple-module synchronization: In order to achieve synchronous operation among multiple boards, all must be provided phase-aligned references. The reference feeds an onboard LMK04832 PLL which operates in nested zero-delay mode to guarantee its outputs are phase aligned with the reference input. If a simple tunable oscillator were used instead, nested zero-delay mode would not be available and multi-board synchronous operation would not be possible.

The LMK can accept an external reference clock operating at up to 750 MHz. If the reference rate exceeds the FPGA SYSREF clock rate (which is limited to < 10 MHz), a phase-aligned synchronization pulse must be presented to the LMK SYNC pin to phase align the LMK outputs of all boards in the system. This is essential to phase-aligned analog I/O across modules. Elk has exposed the LMK SYNC pin from the SOM for this very purpose. If the reference clock rate is less than 10 MHz, the LMK SYNC pin may be ignored.

Standard Features

Power Dissipation

Power dissipation is heavily dependent on the firmware implementation. Typically, using more SERDES channels, more ARM cores and enabling RFdc core will increase power consumption.

The Xilinx power estimator for the supplied firmware design predicts baseline module power consumption to be approximately 16W and to increase modestly when either the SERDES or RFdc cores are switched at full frequency.

When generating sine waves on all DACs and capturing from all ADCs, the SOM+carrier draws Voltage at test point VPWR I: 0.26V Current = (VPWRI/20)/.005 = 2.6A Supply Voltage: 12.17V Power = IV = 2.6A * 12.17V = 31.64W

The RFSoCs report a die temperature of ~55C throughout the test, with the active heatspreader attached.

Software Tools

Software development tools for the module provide comprehensive support via C++ libraries, including device drivers, data buffering, card controls, and utilities that allow developers to be productive from the outset. The FPGA JTAG connector may be controlled using inexpensive USB Digilent debug aids providing compatibility with the Xilinx Platform USB Cable. However more commonly and conveniently, the target may boot PetaLinux and an ethernet connection used to facilitate in-system debugging via the Xilinx target communication framework (TCF).

Logic Tools

High speed DSP, analysis, customized triggering and other unique features may be added to the module by modifying the logic. The Board Support Package (BSP) tool provides support for RTL development. The standard logic provides a hardware interface layer that allows designers to concentrate on the application-specific portions of the design. Designer can build upon the Innovative components for packet handling, hardware interfaces and system functions, the Xilinx IP core library, and third party IP. RTL source for the BSP is provided for customization.